Many different types of test pins and many different I/O cells exist. Often, I/O cells cannot be used for sharing certain types of test pins. The type of special I/Os and the type of different test pins are increasing every day. It is getting very difficult to keep up with these new I/O cells and to ask customers to tune their inputs to test tools so that a proper I/O cell is used for the test pin. Moreover, if the customer overlooks or forgets to follow the restrictions, cost is very high and the IC design may go on proto-hold. Additionally, problems may appear while running pattern generation. A failure to rapidly identify the problem in test sharing may cause a tight schedule or even a delay. Thus, it is desirable to provide a new generic approach for sharing test pins.